2018-09-24 20:43:31 +03:00
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#define ALIGN .align
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.intel_syntax noprefix
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.section .text
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.global cnv2_mainloop_ivybridge_asm
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.global cnv2_mainloop_ryzen_asm
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2018-10-22 23:08:29 +07:00
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.global cnv2_mainloop_bulldozer_asm
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2018-09-25 09:25:47 +03:00
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.global cnv2_double_mainloop_sandybridge_asm
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2018-09-24 20:43:31 +03:00
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ALIGN 16
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cnv2_mainloop_ivybridge_asm:
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2019-01-13 23:00:41 +07:00
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#include "../cn2/cnv2_main_loop_ivybridge.inc"
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2018-09-24 20:43:31 +03:00
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ret 0
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ALIGN 16
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cnv2_mainloop_ryzen_asm:
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2019-01-13 23:00:41 +07:00
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#include "../cn2/cnv2_main_loop_ryzen.inc"
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2018-09-24 20:43:31 +03:00
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ret 0
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2018-09-25 09:25:47 +03:00
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2018-10-22 23:08:29 +07:00
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ALIGN 16
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cnv2_mainloop_bulldozer_asm:
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2019-01-13 23:00:41 +07:00
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#include "../cn2/cnv2_main_loop_bulldozer.inc"
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2018-10-22 23:08:29 +07:00
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ret 0
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2018-09-25 09:25:47 +03:00
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ALIGN 16
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cnv2_double_mainloop_sandybridge_asm:
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2019-01-13 23:00:41 +07:00
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#include "../cn2/cnv2_double_main_loop_sandybridge.inc"
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2018-09-25 09:25:47 +03:00
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ret 0
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